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1 semiconductor june 1998 82c55a cmos programmable peripheral interface features ? pin compatible with nmos 8255a ? 24 programmable i/o pins ? fully ttl compatible ? high speed, no wait state operation with 5mhz and 8mhz 80c86 and 80c88 ? direct bit set/reset capability ? enhanced control word read capability ? l7 process ? 2.5ma drive capability on all i/o ports ? low standby power (iccsb) . . . . . . . . . . . . . . . . .10 m a description the harris 82c55a is a high performance cmos version of the industry standard 8255a and is manufactured using a self-aligned silicon gate cmos process (scaled saji iv). it is a general purpose programmable i/o device which may be used with many different microprocessors. there are 24 i/o pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. the high performance and industry standard con?guration of the 82c55a make it compatible with the 80c86, 80c88 and other microprocessors. static cmos circuit design insures low operating power. ttl compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. the harris advanced saji process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power. ordering information part numbers package temperature range pkg. no. 5mhz 8mhz cp82c55a-5 cp82c55a 40 ld pdip 0 o c to 70 o c e40.6 ip82c55a-5 ip82c55a -40 o c to 85 o c e40.6 CS82C55A-5 cs82c55a 44 ld plcc 0 o c to 70 o c n44.65 is82c55a-5 is82c55a -40 o c to 85 o c n44.65 cd82c55a-5 cd82c55a 40 ld cerdip 0 o c to 70 o c f40.6 id82c55a-5 id82c55a -40 o c to 85 o c f40.6 md82c55a-5/b md82c55a/b -55 o c to 125 o c f40.6 8406601qa 8406602qa smd# f40.6 mr82c55a-5/b mr82c55a/b 44 pad clcc -55 o c to 125 o c j44.a 8406601xa 8406602xa smd# j44.a pinouts 82c55a (dip) top view 82c55a (clcc) top view 82c55a (plcc) top view pa 3 pa 2 pa 1 pa 0 rd cs gnd a1 a0 pc7 pc6 pc5 pc4 pc0 pc1 pc2 pc3 pb0 pb1 pb2 pa 4 pa 5 pa 6 pa 7 wr rese t d0 d1 d2 d3 d4 d5 d6 d7 v cc pb7 pb6 pb5 pb4 pb3 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 40 65 32144434241 4 9 10 11 8 7 12 13 17 16 15 14 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 gnd nc a1 a0 pc7 pc6 pc5 pc4 pc0 pc1 pc2 pc3 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 v cc nc nc reset d0 d1 d2 d3 d4 d5 d6 d7 nc cs rd pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 wr cs gnd a1 a0 pc7 pc6 pc5 pc4 pc0 pc1 pc3 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 nc nc reset d0 d1 d2 d3 d4 d5 d6 d7 v cc rd pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 wr nc pc2 nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 file number 2969.2
2 functional diagram pin description symbol pin number type description v cc 26 v cc : the +5v power supply pin. a 0.1 m f capacitor between pins 26 and 7 is recommended for decoupling. gnd 7 ground d0-d7 27-34 i/o data bus: the data bus lines are bidirectional three-state pins connected to the system data bus. reset 35 i reset: a high on this input clears the control register and all ports (a, b, c) are set to the input mode with the bus hold circuitry turned on. cs 6 i chip select: chip select is an active low input used to enable the 82c55a onto the data bus for cpu communications. rd 5 i read: read is an active low input control signal used by the cpu to read status information or data via the data bus. wr 36 i write: write is an active low input control signal used by the cpu to load control words and data into the 82c55a. a0-a1 8, 9 i address: these input signals, in conjunction with the rd and wr inputs, control the selection of one of the three ports or the control word register. a0 and a1 are normally connected to the least significant bits of the address bus a0, a1. pa0-pa7 1-4, 37-40 i/o port a: 8-bit input and output port. both bus hold high and bus hold low circuitry are present on this port. pb0-pb7 18-25 i/o port b: 8-bit input and output port. bus hold high circuitry is present on this port. pc0-pc7 10-17 i/o port c: 8-bit input and output port. bus hold circuitry is present on this port. group a port a (8) group a port c upper (4) group b port c lower (4) group b port b (8) group b control group a control data bus buffer read write control logic rd wr a1 a0 reset cs d7-d0 power supplies +5v gnd bi-directional data bus i/o pa7-pa0 i/o pc7-pc4 i/o pc3-pc0 i/o pb7-pb0 8-bit internal data bus 82c55a
3 functional description data bus buffer this three-state bi-directional 8-bit buffer is used to interface the 82c55a to the system data bus. data is transmitted or received by the buffer upon execution of input or output instructions by the cpu. control words and status informa- tion are also transferred through the data bus buffer. read/write and control logic the function of this block is to manage all of the internal and external transfers of both data and control or status words. it accepts inputs from the cpu address and control busses and in turn, issues commands to both of the control groups. (cs) chip select. a low on this input pin enables the communcation between the 82c55a and the cpu. (rd) read. a low on this input pin enables 82c55a to send the data or status information to the cpu on the data bus. in essence, it allows the cpu to read from the 82c55a. (wr) write. a low on this input pin enables the cpu to write data or control words into the 82c55a. (a0 and a1) port select 0 and port select 1. these input signals, in conjunction with the rd and wr inputs, control the selection of one of the three ports or the control word register. they are normally connected to the least signi?cant bits of the address bus (a0 and a1). (reset) reset. a high on this input initializes the control register to 9bh and all ports (a, b, c) are set to the input mode. bus hold devices internal to the 82c55a will hold the i/o port inputs to a logic 1 state with a maximum hold current of 400 m a. group a and group b controls the functional con?guration of each port is programmed by the systems software. in essence, the cpu outputs a con- trol word to the 82c55a. the control word contains information such as mode, bit set, bit reset, etc., that ini- tializes the functional con?guration of the 82c55a. each of the control blocks (group a and group b) accepts commands from the read/write control logic, receives control words from the internal data bus and issues the proper commands to its associated ports. control group a - port a and port c upper (c7 - c4) control group b - port b and port c lower (c3 - c0) the control word register can be both written and read as shown in the basic operation table. figure 4 shows the control word format for both read and write operations. when the control word is read, bit d7 will always be a logic 1, as this implies control word mode information. 82c55a basic operation a1 a0 rd wr cs input operation (read) 00010 port a ? data bus 01010 port b ? data bus 10010 port c ? data bus 11010 control word ? data bus output operation (write) 00100 data bus ? port a 01100 data bus ? port b 10100 data bus ? port c 11100 data bus ? control disable function xxxx1 data bus ? three-state x x 1 1 0 data bus ? three-state figure 1. 82c55a block diagram. data bus buffer, read/write, group a & b control logic functions group a port a (8) group a port c upper (4) group b port c lower (4) group b port b (8) group b control group a control data read write control logic rd wr a1 a0 reset cs d7-d0 power supplies +5v gnd bi-directional data bus i/o pa7- i/o pc7- i/o pc3- i/o pb7- buffer bus pb0 pc0 pc4 pa 0 8-bit internal data bus 82c55a
4 ports a, b, and c the 82c55a contains three 8-bit ports (a, b, and c). all can be con?gured to a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and ?exibility of the 82c55a. port a one 8-bit data output latch/buffer and one 8-bit data input latch. both pull-up and pull-down bus-hold devices are present on port a. see figure 2a. port b one 8-bit data input/output latch/buffer and one 8-bit data input buffer. see figure 2b. port c one 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). this port can be divided into two 4-bit ports under the mode control. each 4-bit port con- tains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports a and b. see figure 2b. operational description mode selection there are three basic modes of operation than can be selected by the system software: mode 0 - basic input/output mode 1 - strobed input/output mode 2 - bi-directional bus when the reset input goes high, all ports will be set to the input mode with all 24 port lines held at a logic one level by internal bus hold devices. after the reset is removed, the 82c55a can remain in the input mode with no additional ini- tialization required. this eliminates the need to pullup or pull- down resistors in all-cmos designs. the control word register will contain 9bh. during the execution of the system program, any of the other modes may be selected using a single output instruction. this allows a single 82c55a to service a variety of peripheral devices with a simple software maintenance routine. any port programmed as an output port is initialized to all zeros when the control word is written. figure 2a. port a bus-hold configuration figure 2b. port b and c bus-hold configuration figure 2. bus-hold configuration master reset or mode change internal data in internal data out (latched) external port a pin output mode input mode reset or mode change internal data in internal data out (latched) external port b, c output mode pin p v cc figure 3. basic mode definitions and bus interface data bus 8 i/o b pb7-pb0 4 i/o pc3-pc0 4 i/o c pc7-pc4 8 i/o a pa7-pa0 control bus address bus rd, wr 82c55a d7-d0 a0-a1 cs mode 0 8 i/o b pb7-pb0 control c 8 i/o a pa7-pa0 mode 1 or i/o control or i/o 8 i/o b pb7-pb0 c bi- a pa7-pa0 mode 2 control directional figure 4. mode definition format d7 d6 d5 d4 d3 d2 d1 d0 port c (lower) 1 = input 0 = output port b 1 = input 0 = output mode selection 0 = mode 0 1 = mode 1 group b port c (upper) 1 = input 0 = output port a 1 = input 0 = output mode selection 00 = mode 0 01 = mode 1 group a 1x = mode 2 mode set flag 1 = active control word 82c55a
5 the modes for port a and port b can be separately de?ned, while port c is divided into two portions as required by the port a and port b de?nitions. all of the output registers, including the status ?ip-?ops, will be reset whenever the mode is changed. modes may be combined so that their functional de?nition can be tailored to almost any i/o structure. for instance: group b can be programmed in mode 0 to monitor simple switch closings or display compu- tational results, group a could be programmed in mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. the mode de?nitions and possible mode combinations may seem confusing at ?rst, but after a cursory review of the complete device operation a simple, logical i/o approach will surface. the design of the 82c55a has taken into account things such as ef?cient pc board layout, control signal de?- nition vs. pc layout and complete functional ?exibility to sup- port almost any peripheral device with no external logic. such design represents the maximum use of the available pins. single bit set/reset feature (figure 5) any of the eight bits of port c can be set or reset using a single output instruction. this feature reduces software requirements in control-based applications. when port c is being used as status/control for port a or b, these bits can be set or reset by using the bit set/reset operation just as if they were output ports. interrupt control functions when the 82c55a is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the cpu. the interrupt request signals, generated from port c, can be inhibited or enabled by setting or resetting the associated inte ?ip-?op, using the bit set/reset function of port c. this function allows the programmer to enable or disable a cpu interrupt by a speci?c i/o device without affecting any other device in the interrupt structure. inte flip-flop de?nition (bit-set)-inte is set - interrupt enable (bit-reset)-inte is reset - interrupt disable note: all mask ?ip-?ops are automatically reset during mode se- lection and device reset. operating modes mode 0 (basic input/output). this functional con?guration provides simple input and output operations for each of the three ports. no handshaking is required, data is simply writ- ten to or read from a speci?c port. mode 0 basic functional de?nitions: ? two 8-bit ports and two 4-bit ports ? any port can be input or output ? outputs are latched ? input are not latched ? 16 different input/output con?gurations possible figure 5. bit set/reset format d7 d6 d5 d4 d3 d2 d1 d0 bit set/reset 1 = set 0 = reset bit select 0 bit set/reset flag control word dont care x x x 0 = active 1234567 01010101 00110011 00001111 b0 b1 b2 mode 0 port definition a b group a # group b d4 d3 d1 d0 port a port c (upper) port b port c (lower) 0 0 0 0 output output 0 output output 0 0 0 1 output output 1 output input 0 0 1 0 output output 2 input output 0 0 1 1 output output 3 input input 0 1 0 0 output input 4 output output 0 1 0 1 output input 5 output input 0 1 1 0 output input 6 input output 0 1 1 1 output input 7 input input 1 0 0 0 input output 8 output output 1 0 0 1 input output 9 output input 1 0 1 0 input output 10 input output 1 0 1 1 input output 11 input input 1 1 0 0 input input 12 output output 1 1 0 1 input input 13 output input 1 1 1 0 input input 14 input output 1 1 1 1 input input 15 input input 82c55a
6 mode 0 (basic input) mode 0 (basic output) mode 0 con?gurations control word #0 control word #2 control word #1 control word #3 tra thr trr tir tar trd tdf rd input cs, a1, a0 d7-d0 taw twa twb tww twd tdw wr d7-d0 cs, a1, a0 output 1 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 0 d4 0 d3 0 d2 1 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 0 d4 0 d3 0 d2 1 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 82c55a
7 control word #4 control word #8 control word #5 control word #9 control word #6 control word #10 control word #7 control word #11 mode 0 con?gurations (continued) 1 d7 0 d6 0 d5 0 d4 1 d3 0 d2 0 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 0 d3 0 d2 0 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 0 d4 1 d3 0 d2 0 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 0 d3 0 d2 0 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 0 d4 1 d3 0 d2 1 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 0 d3 0 d2 1 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 0 d4 1 d3 0 d2 1 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 0 d3 0 d2 1 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 82c55a
8 operating modes mode 1 - (strobed input/output). this functional con?gura- tion provides a means for transferring i/o data to or from a speci?ed port in conjunction with strobes or hand shaking signals. in mode 1, port a and port b use the lines on port c to generate or accept these hand shaking signals. mode 1 basic function de?nitions: ? two groups (group a and group b) ? each group contains one 8-bit port and one 4-bit control/data port ? the 8-bit data port can be either input or output. both inputs and outputs are latched. ? the 4-bit port is used for control and status of the 8-bit port. input control signal de?nition (figures 6 and 7) stb (strobe input) a low on this input loads data into the input latch. ibf (input buffer full f/f) a high on this output indicates that the data has been loaded into the input latch: in essence, and acknowledg- ment. ibf is set by stb input being low and is reset by the rising edge of the rd input. control word #12 control word #14 control word #13 control word #15 mode 0 con?gurations (continued) 1 d7 0 d6 0 d5 1 d4 1 d3 0 d2 0 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 1 d3 0 d2 1 d1 0 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 1 d3 0 d2 0 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c 1 d7 0 d6 0 d5 1 d4 1 d3 0 d2 1 d1 1 d0 8 pa7 - pa0 4 pc7 - pc4 4 pc3 - pc0 8 pb7 - pb0 d7 - d0 82c55a a b c figure 6. mode 1 input 1 d7 0 d6 1 d5 1 d4 1/0 d3 d2 d1 d0 control word mode 1 (port a) pc4 8 ibfa pc5 inte a pa7-pa0 stba intra pc3 pc6, pc7 i/o 2 rd pc6, pc7 1 = input 0 = output 1 d7 d6 d5 d4 d3 d2 d1 d0 control word mode 1 (port b) pc2 8 ibfb pc1 inte b pb7-pb0 stbb intrb pc0 rd 11 82c55a
9 intr (interrupt request) a high on this output can be used to interrupt the cpu when and input device is requesting service. intr is set by the condition: stb is a one, ibf is a one and inte is a one. it is reset by the falling edge of rd. this procedure allows an input device to request service from the cpu by simply strobing its data into the port. inte a controlled by bit set/reset of pc4. inte b controlled by bit set/reset of pc2. output control signal de?nition (figure 8 and 9) obf - output buffer full f/f). the obf output will go low to indicate that the cpu has written data out to be speci?ed port. this does not mean valid data is sent out of the part at this time since obf can go true before data is available. data is guaranteed valid at the rising edge of obf, (see note 1). the obf f/f will be set by the rising edge of the wr input and reset by a ck input being low. a ck - acknowledge input). a low on this input informs the 82c55a that the data from port a or port b is ready to be accepted. in essence, a response from the peripheral device indicating that it is ready to accept data, (see note 1). intr - (interrupt request). a high on this output can be used to interrupt the cpu when an output device has accepted data transmitted by the cpu. intr is set when a ck is a one, obf is a one and inte is a one. it is reset by the falling edge of wr. inte a controlled by bit set/reset of pc6. inte b controlled by bit set/reset of pc2. note: 1. to strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. the user needs to send obf to the peripheral device, generates an a ck from the pe- ripheral device and then latch data into the peripheral device on the rising edge of obf. figure 7. mode 1 (strobed input) tst stb intr rd input from ibf peripheral tsib tsit tph tps trit trib figure 8. mode 1 output 1 d7 0 d6 1 d5 1 d4 1/0 d3 d2 d1 d0 control word mode 1 (port a) pc7 8 a cka pc6 pa7-pa0 obfa intra pc3 pc4, pc5 2 wr pc4, pc5 1 = input 0 = output 1 d7 d6 d5 d4 d3 d2 d1 d0 control word mode 1 (port b) pc1 8 a ckb pc2 inte b pb7-pb0 obfb intrb pc0 wr 10 inte a 82c55a
10 operating modes mode 2 (strobed bi-directional bus i/o) the functional con?guration provides a means for communi- cating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus i/o). hand shaking signals are provided to maintain proper bus ?ow discipline similar to mode 1. interrupt gener- ation and enable/disable functions are also available. mode 2 basic functional de?nitions: ? used in group a only ? one 8-bit, bi-directional bus port (port a) and a 5-bit control port (port c) ? both inputs and outputs are latched ? the 5-bit control port (port c) is used for control and status for the 8-bit, bi-directional bus port (port a) bi-directional bus i/o control signal de?nition (figures 11, 12, 13, 14) intr - (interrupt request). a high on this output can be used to interrupt the cpu for both input or output operations. output operations obf - (output buffer full). the obf output will go low to indicate that the cpu has written data out to port a. a ck - (acknowledge). a low on this input enables the three-state output buffer of port a to send out the data. oth- erwise, the output buffer will be in the high impedance state. inte 1 - (the inte ?ip-?op associated with obf). con- trolled by bit set/reset of pc4. input operations stb - (strobe input). a low on this input loads data into the input latch. ibf - (input buffer full f/f). a high on this output indicates that data has been loaded into the input latch. inte 2 - (the inte ?ip-?op associated with ibf). controlled by bit set/reset of pc4. figure 9. mode 1 (strobed output) twob twb tak tait taob twit obf wr intr a ck output combinations of mode 1: port a and port b can be individually de?ned as input or output in mode 1 to support a wide variety of strobed i/o applications. figure 10. combinations of mode 1 1 d7 0 d6 1 d5 1 d4 1/0 d3 d2 d1 d0 control word port a - (strobed input) pc4 8 obfb pa7-pa0 stba intrb pc0 pc6, pc7 2 wr pc6, pc7 1 = input 0 = output port b - (strobed output) 8 iibfa pc5 intra pc3 a ckb pc2 i/o pc1 pb7, pb0 rd 10 1 d7 0 d6 1 d5 0 d4 1/0 d3 d2 d1 d0 control word port a - (strobed output) pc7 8 stbb pa7-pa0 obfa intrb pc0 pc4, pc5 2 rd pc4, pc5 1 = input 0 = output port b - (strobed input) 8 a cka pc6 intra pc3 ibfb pc1 i/o pc2 pb7, pb0 wr 11 82c55a
11 figure 11. mode control word figure 12. mode 2 note: any sequence where wr occurs before a ck and stb occurs before rd is permissible. (intr = ibf mask stb rd ? obf mask a ck wr) figure 13. mode 2 (bi-directional) 1 d7 d6 d5 d4 d3 d2 d1 d0 control word 1/0 1/0 1 1/0 pc2-pc0 1 = input 0 = output port b 1 = input 0 = output group b mode 0 = mode 0 1 = mode 1 pc7 obfa pc6 inte pa7-pa0 a cka ibfa pc4 wr inte rd pc3 pc5 pc2-pc0 1 2 8 stba 3 i/o intra twob taob tak tad tkd tph tps tsib tst obf wr intr a ck ibf stb peripheral bus rd trib data from peripheral to 82c55a data from 82c55a to peripheral data from 82c55a to cpu data from cpu to 82c55a 82c55a
12 mode 2 and mode 0 (input) mode 2 and mode 0 (output) mode 2 and mode 1 (output) mode 2 and mode 1 (input) figure 14. mode 2 combinations 1 d7 1 d6 d5 d4 d3 d2 d1 d0 control word pc7 8 stba pa7-pa0 obfa ibfa pc5 pc2-pc0 3 rd pc2-pc0 1 = input 0 = output a cka pc6 intra pc3 i/o pc4 pb7-pb0 01 1/0 8 wr 1 d7 1 d6 d5 d4 d3 d2 d1 d0 control word pc7 8 stba pa7-pa0 obfa ibfa pc5 pc2-pc0 3 rd pc2-pc0 1 = input 0 = output a cka pc6 intra pc3 i/o pc4 pb7, pb0 00 1/0 8 wr 1 d7 1 d6 d5 d4 d3 d2 d1 d0 control word pc7 8 stba pa7-pa0 obfa ibfa pc5 rd a cka pc6 intra pc3 pc4 pb7-pb0 10 8 wr pc1 obfb a ckb pc2 pc0 intrb 1 d7 1 d6 d5 d4 d3 d2 d1 d0 control word pc7 8 stba pa7-pa0 obfa ibfa pc5 rd a cka pc6 intra pc3 pc4 pb7-pb0 11 8 wr pc2 stbb pc1 pc0 intrb ibfb 82c55a
13 special mode combination considerations there are several combinations of modes possible. for any combination, some or all of port c lines are used for control or status. the remaining bits are either inputs or outputs as de?ned by a set mode command. during a read of port c, the state of all the port c lines, except the a ck and stb lines, will be placed on the data bus. in place of the a ck and stb line states, ?ag status will appear on the data bus in the pc2, pc4, and pc6 bit positions as illustrated by figure 17. through a write port c command, only the port c pins programmed as outputs in a mode 0 group can be written. no other pins can be affected by a write port c command, nor can the interrupt enable ?ags be accessed. to write to any port c output programmed as an output in mode 1 group or to change an interrupt enable ?ag, the set/reset port c bit command must be used. with a set/reset port cea bit command, any port c line programmed as an output (including ibf and obf) can be written, or an interrupt enable ?ag can be either set or reset. port c lines programmed as inputs, including a ck and stb lines, associated with port c fare not affected by a set/reset port c bit command. writing to the correspond- ing port c bit positions of the a ck and stb lines with the set reset port c bit command will affect the group a and group b interrupt enable ?ags, as illustrated in figure 17. current drive capability any output on port a, b or c can sink or source 2.5ma. this feature allows the 82c55a to directly drive darlington type drivers and high-voltage displays that require such sink or source current. mode definition summary mode 0 mode 1 mode 2 in out in out group a only pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 in in in in in in in in out out out out out out out out in in in in in in in in out out out out out out out out pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 in in in in in in in in out out out out out out out out in in in in in in in in out out out out out out out out pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 in in in in in in in in out out out out out out out out intrb ibfb stbb intra stba ibfa i/o i/o intrb obfb a ckb intra i/o i/o a cka obfa i/o i/o i/o intra stba ibfa a cka obfa mode 0 or mode 1 only input configuration d7 d6 d5 d4 d3 d2 d1 d0 i/o i/o ibfa intea intra inteb ibfb intrb output configuration d7 d6 d5 d4 d3 d2 d1 d0 obfa intea i/o i/o intra inteb obfb intrb figure 15. mode 1 status word format d7 d6 d5 d4 d3 d2 d1 d0 obfa inte1 ibfa inte2 intra x x x (de?ned by mode 0 or mode 1 selection) figure 16. mode 2 status word format group a group b group a group b group a group b 82c55a
14 reading port c status (figures 15 and 16) in mode 0, port c transfers data to or from the peripheral device. when the 82c55a is programmed to function in modes 1 or 2, port c generates or accepts hand shaking signals with the peripheral device. reading the contents of port c allows the programmer to test or verify the status of each peripheral device and change the program ?ow accordingly. there is not special instruction to read the status information from port c. a normal read operation of port c is executed to perform this function. applications of the 82c55a the 82c55a is a very powerful tool for interfacing peripheral equipment to the microcomputer system. it represents the optimum use of available pins and ?exible enough to inter- face almost any i/o device without the need for additional external logic. each peripheral device in a microcomputer system usually has a service routine associated with it. the routine manages the software interface between the device and the cpu. the functional de?nition of the 82c55a is programmed by the i/o service routine and becomes an extension of the system software. by examining the i/o devices interface characteristics for both data transfer and timing, and matching this information to the examples and tables in the detailed operational description, a control word can easily be developed to initialize the 82c55a to exactly ?t the application. figures 18 through 24 present a few examples of typical applications of the 82c55a. interrupt enable flag position alternate port c pin signal (mode) inte b pc2 a ckb (output mode 1) or stbb (input mode 1) inte a2 pc4 stba (input mode 1 or mode 2) inte a1 pc6 a cka (output mode 1 or mode 2) figure 17. interrupt enable flags in modes 1 and 2 figure 18. printer interface pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc7 pc6 pc5 pc4 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc1 pc2 data ready ack paper feed forward/rev. data ready ack paper feed forward/rev. ribbon carriage sen. mode 1 (output) 82c55a mode 1 (output) control logic and drivers interrupt request pc0 interrupt request pc3 hammer relays high speed printer 82c55a
15 figure 19. keyboard and display interface figure 20. keyboard and terminal address interface figure 21. digital to analog, analog to digital figure 22. basic crt controller interface pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc1 pc2 strobe ack data ready ack mode 1 (output) 82c55a mode 1 (input) fully decoded interrupt request interrupt request pc3 pc6 pc7 keyboard r0 r1 r2 r3 r4 r5 shift control b0 b1 b2 b3 b4 b5 backspace clear burroughs self-scan display blanking cancel word strobe ack fully decoded keyboard r0 r1 r2 r3 r4 r5 shift control pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pc6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 mode 0 (input) 82c55a mode 1 (input) pc3 bust lt test lt terminal address interrupt request pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pc6 pc7 pc1 pc2 pc3 pb0 pb1 pb2 pc4 pc5 lsb stb data mab mode 0 (input) 82c55a mode 0 (output) 12-bit a/d converter (dac) pc0 pb3 pc6 pc7 bit set/reset sample en stb lsb 8-bit d/a converter (adc) analog input analog output pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc7 pc6 pc5 pc4 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc2 pc1 mode 0 (output) 82c55a mode 1 (output) pc3 data ready ack crt controller character gen. interrupt request refresh buffer r0 r1 r2 r3 r4 r5 shift control row stb column stb cursor h/v stb cursor/row/column cursor control pc0 address h&v blanked black/white 82c55a
16 figure 23. basic floppy disc interface figure 24. machine tool controller interface pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pc7 pc6 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc1 pc0 mode 0 (output) 82c55a mode 2 pc3 data stb ack (in) floppy disk interrupt request d0 d1 d2 d3 d4 d5 d6 d7 track 0 sensor sync ready index data ready ack (out) pc2 engage head forward/rev. read enable write enable disc select enable crc test busy lt controller and drive pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pc6 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc1 pc2 mode 0 (output) 82c55a mode 1 pc3 stb a ck b level interrupt request r0 r1 r2 r3 r4 r5 r6 r7 start/stop limit sensor (h/v) out of fluid stop/go pc0 change tool left/right up/down hor. step strobe vert. step strobe slew/step fluid enable emergency stop paper tape reader (input) machine tool mode 0 (input) 82c55a
17 absolute maximum ratings t a = 25 o c thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 5.5v operating temperature range c82c55a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c i82c55a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c m82c55a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) q ja q jc cerdip package . . . . . . . . . . . . . . . . 50 o c/w 10 o c/w clcc package . . . . . . . . . . . . . . . . . . 65 o c/w 14 o c/w pdip package . . . . . . . . . . . . . . . . . . . 50 o c/w n/a plcc package . . . . . . . . . . . . . . . . . . 46 o c/w n/a maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum junction temperature cdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (plcc lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations v cc = 5.0v 10%; t a = 0 o c to +70 o c (c82c55a); t a = -40 o c to +85 o c (i82c55a); t a = -55 o c to +125 o c (m82c55a) symbol parameter limits units test conditions min max v ih logical one input voltage 2.0 2.2 - v i82c55a, c82c55a, m82c55a v il logical zero input voltage - 0.8 v v oh logical one output voltage 3.0 v cc -0.4 -vi oh = -2.5ma, i oh = -100 m a v ol logical zero output voltage - 0.4 v i ol +2.5ma i i input leakage current -1.0 +1.0 m av in = v cc or gnd, dip pins: 5, 6, 8, 9, 35, 36 io i/o pin leakage current -10 +10 m a vo = v cc or gnd dip pins: 27 - 34 ibhh bus hold high current -50 -400 m a vo = 3.0v. ports a, b, c ibhl bus hold low current 50 400 m a vo = 1.0v. port a only idar darlington drive current -2.5 note 2, 4 ma ports a, b, c. test condition 3 iccsb standby power supply current - 10 m av cc = 5.5v, v in = v cc or gnd. output open iccop operating power supply current - 1 ma/mhz t a = +25 o c, v cc = 5.0v, typical (see note 3) notes: 2. no internal current limiting exists on port outputs. a resistor must be added externally to limit the current. 3. iccop = 1ma/mhz of peripheral read/write cycle time. (example: 1.0 m s i/o read/write cycle time = 1ma). 4. tested as v oh at -2.5ma. capacitance t a = 25 o c symbol parameter typical units test conditions cin input capacitance 10 pf freq = 1mhz, all measurements are referenced to device gnd ci/o i/o capacitance 20 pf 82c55a
18 ac electrical speci?cations v cc = +5v 10%, gnd = 0v; t a = -55 o c to +125 o c (m82c55a) (m82c55a-5); t a = -40 o c to +85 o c (i82c55a) (i82c55a-5); t a = 0 o c to +70 o c (c82c55a) (c82c55a-5) symbol parameter 82c55a-5 82c55a units test conditions min max min max read timing (1) tar address stable before rd 0-0-ns (2) tra address stable after rd 0-0-ns (3) trr rd pulse width 250 - 150 - ns (4) trd data valid from rd - 200 - 120 ns 1 (5) tdf data float after rd 10 75 10 75 ns 2 (6) trv time between rds and/or wrs 300 - 300 - ns write timing (7) taw address stable before wr 0-0-ns (8) twa address stable after wr 20 - 20 - ns (9) tww wr pulse width 100 - 100 - ns (10) tdw data valid to wr high 100 - 100 - ns (11) twd data valid after wr high 30 - 30 - ns other timing (12) twb wr = 1 to output - 350 - 350 ns 1 (13) tir peripheral data before rd 0-0-ns (14) thr peripheral data after rd 0-0-ns (15) tak ack pulse width 200 - 200 - ns (16) tst stb pulse width 100 - 100 - ns (17) tps peripheral data before stb high 20 - 20 - ns (18) tph peripheral data after stb high 50 - 50 - ns (19) tad ack = 0 to output - 175 - 175 ns 1 (20) tkd ack = 1 to output float 20 250 20 250 ns 2 (21) twob wr = 1 to obf = 0 - 150 - 150 ns 1 (22) taob ack = 0 to obf = 1 - 150 - 150 ns 1 (23) tsib stb = 0 to ibf = 1 - 150 - 150 ns 1 (24) trib rd = 1 to ibf = 0 - 150 - 150 ns 1 (25) trit rd = 0 to intr = 0 - 200 - 200 ns 1 (26) tsit stb = 1 to intr = 1 - 150 - 150 ns 1 (27) tait ack = 1 to intr = 1 - 150 - 150 ns 1 (28) twit wr = 0 to intr = 0 - 200 - 200 ns 1 (29) tres reset pulse width 500 - 500 - ns 1, (note) note: period of initial reset pulse after power-on must be at least 50 m sec. subsequent reset pulses may be 500ns minimum. 82c55a
19 timing waveforms figure 25. mode 0 (basic input) figure 26. mode 0 (basic output) figure 27. mode 1 (strobed input) tra (2) thr (14) trr (3) tir (13) tar (1) trd (4) tdf (5) rd input cs, a1, a0 d7-d0 taw (7) twa (8) tws (12) tww (9) twd (11) tdw wr d7-d0 cs, a1, a0 output (10) tst (16) stb intr rd input from ibf peripheral tsib tsit tph tps (17) trit trib (24) (23) (26) (25) (18) 82c55a
20 figure 28. mode 1 (strobed output) figure 29. mode 2 (bi-directional) note: any sequence where wr occurs before a ck and stb occurs before rd is permissible. (intr = ibf mask stb rd obf mask a ck wr) timing waveforms (continued) twob (21) twb (12) tak (15) tait (27) taob (22) twit obf wr intr a ck output (28) twob taob tak tad (19) tkd tph (18) tps (17) tsib tst obf wr intr a ck ibf stb peripheral bus rd trib (24) data from peripheral to 82c55a data from 82c55a to peripheral data from 82c55a to cpu data from cpu to 82c55a (21) (22) (15) (16) (20) (23) (note) (note) 82c55a
21 ac test circuit ac testing input, output waveforms burn-in circuits figure 30. write timing figure 31. read timing timing waveforms (continued) wr data a0-a1, cs bus tww (9) tdw (10) twd (11) twa (8) taw (7) rd data a0-a1, cs bus trr (3) tra (2) tar (1) valid (4) trd tdf (5) high impedance r1 v1 output from device under test note: includes stray and jig capacitance test point c1 r2 (see note) test condition definition table test condition v1 r1 r2 c1 1 1.7v 523 w open 150pf 2v cc 2k w 1.7k w 50pf 3 1.5v 750 w open 50pf input vih + 0.4v vil - 0.4v 1.5v 1.5v voh vol output ac testing: all ac parameters tested as per test circuits. input rise and fall times are driven at 1ns/v. md82c55a cerdip notes: 1. v cc = 5.5v 0.5v 2. vih = 4.5v 10% 3. vil = -0.2v to 0.4v 4. gnd = 0v mr82c55a clcc notes: 1. c1 = 0.01 m f minimum 2. all resistors are 47k w 5% 3. f0 = 100khz 10% 4. f1 = f0 ? 2; f2 = f1 ? 2; . . . ; f15 = f14 ? 2 f7 f8 f9 f4 f3 gnd f0 f1 f10 f6 f7 f8 f9 f6 f7 f8 f9 f10 f6 33 34 35 36 37 38 40 32 31 30 29 24 25 26 27 28 21 22 23 13 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 39 1 f12 f13 f14 f2 f5 f15 f11 f12 f13 f14 f15 f11 f12 v cc f13 f14 f15 f11 f12 f11 c1 f10 v cc f13 f14 f10 f9 f8 f7 f12 f11 f15 gnd f0 f10 f6 f7 f8 f9 f10 f6 f1 14 13 12 11 10 9 8 7 17 16 15 2 5 30 35 39 38 37 36 33 34 32 31 29 4 6 3 1 40 41 42 43 44 28 27 26 25 24 23 22 21 20 19 18 f3 f4 f9 f8 f12 f13 f14 f2 f5 f15 f12 f13 f14 f15 f11 f12 f11 f11 f6 f7 c1 82c55a
22 die characteristics die dimensions: 95 x 100 x 19 1mils metallization: type: silicon - aluminum thickness: 11k ? 1k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: 0.78 x 10 5 a/cm 2 metallization mask layout 82c55a rd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 wr cs gnd a1 a0 pc7 pc6 pc5 pc4 pc0 pc1 pc2 pd3 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 v cc d7 d6 d5 d4 d3 d2 d1 d0 reset 82c55a
23 82c55a dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e40.6 (jedec ms-011-ac issue b) 40 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.980 2.095 50.3 53.2 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n40 409 rev. 0 12/93
24 82c55a plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. converted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allow- able mold protrusion is 0.010 inch (0.25mm) per side. dimen- sions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. n is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view a d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view a typ. 0.004 (0.10) c -c- d2/e2 c l n44.65 (jedec ms-018ac issue a) 44 lead plastic leaded chip carrier package sym- bol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.685 0.695 17.40 17.65 - d1 0.650 0.656 16.51 16.66 3 d2 0.291 0.319 7.40 8.10 4, 5 e 0.685 0.695 17.40 17.65 - e1 0.650 0.656 16.51 16.66 3 e2 0.291 0.319 7.40 8.10 4, 5 n44 446 rev. 2 11/97
25 82c55a ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- a d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa c a - b m d s s e a f40.6 mil-std-1835 gdip1-t40 (d-5, configuration a) 40 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 2.096 - 53.24 5 e 0.510 0.620 12.95 15.75 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.070 0.38 1.78 6 s1 0.005 - 0.13 - 7 a 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n40 408 rev. 0 4/94
26 82c55a ceramic leadless chip carrier packages (clcc) d j x 45 o d3 b h x 45 o a a1 e l l3 e b3 l1 d2 d1 e 1 e2 e1 l2 plane 2 plane 1 e3 b2 0.010 e h s s 0.010 e f s s -e- 0.007 e f m s hs b1 -h- -f- j44.a mil-std-1835 cqcc1-n44 (c-5) 44 pad ceramic leadless chip carrier package symbol inches millimeters notes min max min max a 0.064 0.120 1.63 3.05 6, 7 a1 0.054 0.088 1.37 2.24 - b 0.033 0.039 0.84 0.99 4 b1 0.022 0.028 0.56 0.71 2, 4 b2 0.072 ref 1.83 ref - b3 0.006 0.022 0.15 0.56 - d 0.640 0.662 16.26 16.81 - d1 0.500 bsc 12.70 bsc - d2 0.250 bsc 6.35 bsc - d3 - 0.662 - 16.81 2 e 0.640 0.662 16.26 16.81 - e1 0.500 bsc 12.70 bsc - e2 0.250 bsc 6.35 bsc - e3 - 0.662 - 16.81 2 e 0.050 bsc 1.27 bsc - e1 0.015 - 0.38 - 2 h 0.040 ref 1.02 ref 5 j 0.020 ref 0.51 ref 5 l 0.045 0.055 1.14 1.40 - l1 0.045 0.055 1.14 1.40 - l2 0.075 0.095 1.90 2.41 - l3 0.003 0.015 0.08 0.38 - nd 11 11 3 ne 11 11 3 n44 443 rev. 0 5/18/94 notes: 1. metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. unless otherwise speci?ed, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. symbol n is the maximum number of terminals. symbols nd and ne are the number of terminals along the sides of length d and e, respectively. 4. the required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. the corner shape (square, notch, radius, etc.) may vary at the manufacturers option, from that shown on the drawing. 6. chip carriers shall be constructed of a minimum of two ceramic layers. 7. dimension a controls the overall package thickness. the maxi- mum a dimension is package height before being solder dipped. 8. dimensioning and tolerancing per ansi y14.5m-1982. 9. controlling dimension: inch.

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